Technical Field
The present invention relates to a semiconductor device fabrication method and a semiconductor device.
Related Art
In a power semiconductor device in which current flows in a thickness direction of a semiconductor wafer (substrate)—such as an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a diode or the like—that is, a power semiconductor device with an electrode at a rear surface of the semiconductor substrate, an inherent resistance component due to the thickness of the semiconductor substrate cannot be disregarded. Accordingly, to avoid deterioration in on-characteristics or off-characteristics of the semiconductor device due to the thickness of the semiconductor substrate, the application of thinning processing to the semiconductor substrate, to make the thickness of the semiconductor substrate thinner, is needed.
Japanese Patent Application Laid-Open (JP-A) No. 2012-174956 discloses a technology in which, in thinning processing of the semiconductor substrate of a power semiconductor device such as an IGBT or the like, mechanical grinding is applied by backgrinding or the like to the rear surface of the semiconductor substrate, at which a front surface structure has been formed, and then chemical grinding such as wet etching or the like is applied in order to remove machining stresses introduced by the mechanical grinding.
JP-A No. 2011-151350 discloses a technology in which a mixed chemical solution of hydrofluoric acid, nitric acid, sulfuric acid and phosphoric acid is used as a chemical solution for grinding by wet etching of the rear surface of a silicon substrate, after a front face structure has been formed.
JP-A No. 2011-204716 discloses a technology in which, in a process of fabrication of a trench gate-type IGBT, boron is implanted into the rear surface of a semiconductor substrate at which a front face structure has been formed, and then the implanted boron is activated by laser annealing.
In the related art as described above, a technology of forming a front face structure and then grinding the rear surface of a semiconductor substrate, a technology of wet etching a rear surface in order to remove a layer damaged by rear surface grinding, and a technology of laser annealing to activate impurities implanted at a rear surface have been respectively partially disclosed.
The rear surface grinding disclosed in JP-A No. 2012-174956 is a basic technology of thinning processing for reducing the resistance of a semiconductor substrate. Meanwhile, rear surface wet etching is a technology that removes a damaged layer of a semiconductor substrate caused by mechanical grinding such as backgrinding or the like, and is required, for example, to prevent cracking of the semiconductor substrate in conveyance operations subsequent to the thinning processing.
With the mixed chemical solution for wet etching disclosed in JP-A No. 2011-151350, the etching progresses by the nitric acid (HNO3) oxidizing the silicon substrate and the hydrofluoric acid (HF) removing the silicon oxide. The phosphoric acid (H3PO4) in the mixed chemical solution has the effect of self-consistently (anisotropically) reducing surface irregularities of the silicon substrate, and is effective for increasing the strength of the silicon substrate.
That is, the phosphoric acid pools in indented portions of the irregularities caused by mechanical grinding or the like, reduces the etching rate (etching speed) of the indented portions, and produces a difference from the etching rate of projecting portions. Thus, the phosphoric acid may produce a smooth mirror finish.
Hence, a silicon substrate rear surface with a mirror finish is in an ideal state for the formation of a rear surface metal electrode by vapor deposition, sputtering or the like.
In the activation of implanted impurities by laser annealing disclosed in JP-A No. 2011-204716, local impurity regions may be formed and a density profile may be precisely controlled. Thus, this is an important technology for facilitating the design of density profiles in order to improve the performance of semiconductor devices.
The respective steps of rear surface grinding, wet etching and laser annealing that are partially disclosed in the above-mentioned references are for solving respective problems in thinning processing of a semiconductor substrate for a power semiconductor device such as an IGBT or the like, in which current is to flow in the thickness direction of the semiconductor substrate. That is, the semiconductor substrate is reduced in thickness and lowered in resistance, measures are taken to counter a reduction in strength of the semiconductor substrate caused by the thinning, and density profile design in order to improve performance is facilitated.
Thus, a series of steps of the rear surface grinding, wet etching and laser annealing of the related art are basic steps in a semiconductor substrate thinning process.
Meanwhile, for IGBTs, further improvements in technologies that reduce a switching loss at a turn-off time (which may be denoted with the symbol “Eoff” hereinafter) are required. The term “switching loss at a turn-off time” used herein is intended to include a loss due to current flowing between the emitter and the collector of an IGBT in the moment after the gate voltage is turned off.
FIG. 1 is a schematic diagram showing a relationship between a Vce(sat)-Eoff characteristic and collector density. Here, Vce(sat) is the voltage between the collector and emitter in the saturation region. As shown in FIG. 1, when the collector density is lower, Vce(sat) rises but Eoff tends to decrease. This is thought to be because, while there is a trade-off of Vce(sat) rising when the collector density is lower, an effect of minority carriers becoming easier to free arises and this contributes to the decrease in Eoff.
Thus, to reduce Eoff, the impurity density in the collector region of an IGBT must be lowered. In particular, for a next-generation IGBT it is considered necessary to lower the P+ collector density of a P-type collector to around 5×1017 atoms/cm3.
However, as described above, phosphoric acid is necessarily included in the chemical solution of the wet etching in the semiconductor substrate thinning process. Thus, when the rear surface wet etching has finished, phosphorus that was contained in the etching solution remains at the surface of the semiconductor substrate.
If this phosphorus is not completely removed by usual deionized water (purified water) washing and impurities are activated by laser annealing in the following stage with the phosphorus still present, the phosphorus is activated as an N-type impurity. In consequence, the density profile of the P-type collector shifts away from design values, which causes deterioration in characteristics of the semiconductor device.
As a practical example, FIG. 2 is a graph showing results of an analysis with a secondary ion-microprobe mass spectrometer (SIMS) of a silicon substrate specimen that has been wet-etched with a mixed chemical solution of hydrofluoric acid, nitric acid and phosphoric acid and, after rinse-washing with purified water, has been subjected to laser annealing.
In the example shown in FIG. 2, undesired phosphorus is detected with a density of around 2×1017 atoms/cm3 to a depth of around 0.4 μm from the rear surface of the wet-etched silicon substrate.
This indicates that the phosphorus included in the chemical solution in the wet etching step adheres to the rear surface of the silicon substrate, and that the residual phosphorus adhering to the rear surface of the silicon substrate in the wet etching step is not completely removed by the rinse-washing with purified water after the wet etching. It also indicates that the residual phosphorus adhering to the rear surface of the silicon is subsequently diffused to a depth of 0.4 μm by the laser annealing.
The phosphorus density of around 2×1017 atoms/cm3 corresponds to 40% of a target impurity density of 5×1017 atoms/cm3 (of, for example, boron 11B+) for a P-type collector.
Because this phosphorus dispersed in the silicon substrate acts as N-type impurities, the phosphorus functions as a counter-dopant against the P-type impurities in the P-type collector of, for example, an IGBT. This leads to variations in the P-type collector density of the IGBT and disrupts precise design of impurity densities, thus hindering a reduction in Eoff.
Thus, how phosphorus that adheres during wet etching can be assuredly removed is a question affecting further improvements in the characteristics of IGBTs.